Topical area C:
Device technology and scalability

Topical area C

The insights obtained in topical areas A and B provide the understanding required to devise electronics based upon resistive switching phenomena. The impact of these devices will depend upon the potential for miniaturisation. This scaling will affect the device parameters and will eventually encounter inherent physical limits. In topical area C, we explore nanotechnological approaches to fabricate highly scaled resistively switching cells including promising routes to engineer the active defects. We will introduce new device approaches, and we will elucidate the technological and physical limits of scaling.

For resistive nanoswitches, a reduction of power consumption is a key goal. In PC memories, the transformation from the crystalline to the amorphous state requires melting, i.e. a process that requires significant power. Hence, a storage mechanism which circumvents melting is highly attractive. Indeed, recent studies imply that in interfacial phase change memories a phase transition can be realised which does not involve melting. While the reported reduction in power consumption is remarkable, the different models proposed to explain the effect are incompatible. We plan to obtain an extensive set of experimental data to correlate the switching energy with the atomic arrangement in these memories.

These activities will be complemented by device design for new computational concepts such as neuromorphic architectures. The next step will be to apply this basic logic-in-memory approach to large-scale crossbar arrays. Therefore, VC-type CRS cells based on TaOx and HfOx devices will be integrated in nanoscale arrays, using the HNF of the Forschungszentrum Jülich. Moreover, as an easy-to-manufacture approach, these nano-crossbar arrays will be used to realise beyond-von-Neumann computing-in-memory concepts, starting with the recently developed CRS adder approach. An alternative way is to implement integrated capacitive associative networks using the non-destructive read-out feature of CRS cells. Those arrays enable energy-efficient and ultra-fast pattern recognition tasks, which are widely required for neuromorphic applications. Besides using CRS cells as binary synapses, we will also explore the construction of hybrid CMOS/ReRAM synaptic circuits mimicking real biological synaptic behaviour more realistically. This work will be performed in close collaboration with the Institute for Neuroscience and Medicine at the Forschungszentrum Jülich and the EECS at RWTH Aachen University.

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